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Application Note 9910
TABLE 1. JUMPER CONFIGURATION
JUMPER
JP1
TYPE
On/Off
POSITION
On
DEFAULT
Off
FUNCTION
Enables SYNCO as the CAS-SYNC0 J3-39 Output.
Off
Disables SYNCO as the CAS-SYNC0 J3-39 Output.
JP2
On/Off
On
Off
Enables UPDA as the CAS-SYNC0 J3-39 Output.
Off
Disables UPDA as the CAS-SYNC0 J3-39 Output.
JP3
3-Point
Off
2-3
Disables the 217-CLK Input
1-2
2-3
Enables BIT-CLK as the 217-CLK Input
Enables CLK2 as the 217-CLK Input
JP4 (Note)
3-Point
Off
2-3
Disables the BIT-CLK Input
1-2
2-3
Enables the input of BIT-CLK from the CAS-OUT-CLK J3-19.
Enables the output of CLK3 to the CAS-OUT-CLK J3-19.
JP5 (Note)
3-Point
Off
2-3
Disables the BIT-CLK Input
1-2
2-3
INVALID
Enables the U6 or J11 CLK Input.
JP6 (Note)
3-Point
Off
2-3
Disables the CAS-IN-CLK Input
1-2
2-3
Enables the 50 ? termination through R13.
Enables the output of CLK3 as the CAS-IN-CLK J1-19.
JP7
3-Point
Off
2-3
25-50MHz Frequency Range Select for prog. clk
1-2
2-3
15-30 MHz Frequency Range Select for prog. clk
40-110 MHz Frequency Range Select for prog. clk
JP8
3-Point
Off
Off
Selects Normal Mode for CPLD-PROG
1-2
2-3
Selects Program Mode for CPLD-PROG
Selects Normal Mode for CPLD-PROG
JP9
3-Point
Off
1-2
Disables the DAC-CLK Input Signal
1-2
2-3
Enables CLK as the DAC-CLK Input signal
Enables ISTRB as the DAC-CLK Input Signal
JP10
3-Point
Off
Off
Select “0” for BADDR3
1-2
2-3
Select “0” for BADDR3
Select “1” for BADDR3
JP11
3-Point
Off
Off
Select “0” for BADDR2
1-2
2-3
Select “0” for BADDR2
Select “1” for BADDR2
JP12
3-Point
Off
Off
Select “0” for BADDR1
1-2
2-3
Select “0” for BADDR1
Select “1” for BADDR1
JP13
3-Point
Off
Off
Select “0” for BADDR0
1-2
2-3
Select “0” for BADDR0
Select “1” for BADDR0
J9-13 to J9-14
On/Off
On
On
Selects TDO-CPLD for TDO.
Of
TDO Not Routed on Board.
NOTE: Jumpers 4-6 have other possible combinations, as detailed on the schematic for Master/Slave configurations of multiple evaluation CCAs.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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